The microelectronics industry had developed exponentially following the Moore’s law,^[1] until the 2010s when the technological challenge is overwhelming to continuing shrinking down the transistor node size. Moreover, the improvement of processor performance cannot keep proportional to the enlargement of the number/density of transistors,^[2] and the ever decreasing size of the transistors leads to the emergence of quantum tunneling effects, and increased energy consumption. It has been widely accepted that the Moore’s law has ended.^[3] Silicon (Si) photonics is one of the most promising routes for “more than Moore” by utilizing photons instead of electrons to transmit and/or process information.^[4] Under extensive research and investment, Si photonics has been developing rapidly and most of the optical/optoelectronic components, including the Si-based optical waveguides,^[5] switches,^[6] modulators,^[7] detectors,^[8] etc. have already been close to mature, leaving the light sources as the primary bottleneck since Si is an indirect bandgap semiconductor with very low light emission efficiency.

Extensive efforts have been put in inventing and developing Si-based light sources, especially lasers. Although lasers made from Si and other group IV semiconductors have achieved significant processes, such as the silicon Raman laser^[9] and the GeSn laser,^[10] they are still far from competing with the commercial GaAs and InP-based group III–V compound lasers. Direct mounting of processed laser, wafer bonding, and direct hetero-epitaxial growth of III–V template/devices on Si are the main-stream technologies to integrate III–V lasers on Si.^[11] Direct mounting promises superior laser performances and good thermal dissipation, while the main problem is high precision alignment with Si waveguide and difficulty to realize high density integration. Monolithically growing III–V lasers directly on Si substrate is a straightforward technical route promising high density and low-cost lasers without complex processing procedures. For example, the Si-based InAs/GaAs quantum dot lasers have made tremendous progresses in recent years.^[12] However, due to the crystal type, lattice constant and thermal expansion coefficient mismatches, the monolithic III–V lasers on Si commonly have a high density of structural defects, such as antiphase domains and dislocations, and face reliability and lifetime problems. Wafer bonding (including wafer-to-wafer and die-to-wafer bonding) is not subject to crystal type and lattice mismatch problems. Furthermore, the directly laser bonding to a Si circuit eliminates the alignment problem and allows a high integration density. Although complex fabrication processes are required for wafer bonding, it is the most successful technical route up to date.

Ion-slicing can be viewed as one type of wafer bonding technologies, by which, light element ions (e.g., H, He) are first implanted into a III–V wafer, then, the III–V wafer is boned to a Si or Si-on-insulator (SOI) wafer, and finally the majority of the III–V wafer is split after post-annealing, resulting in a III–V thin film template on Si/SOI (III–VOI) wafer. Recently, our group has demonstrated high-quality 2-inch (1 inch = 2.54 cm) InP-on-insulator-Si (InPOI) wafers through a novel ion-slicing technique with sequential He and H ion implantation at room temperature.^[13] The InPOI wafers were later used as substrates to grow optoelectronic devices by molecular beam epitaxy (MBE). Local delamination phenomenon was observed for certain samples after MBE growth. An Al₂O₃ layer was later introduced between the InP and the SiO₂ layer with the intention of improving adherence. GaAs-on-insulator-Si (GaAsOI) wafer was successfully demonstrated with the same technique (the results will be published elsewhere). After MBE growth, the delamination problem remains. Figure 1(a) shows an example of a GaAsOI surface with delamination after deoxidation at about 600°C. The materials involved in the III–VOI structures have different thermal expansion coefficients. The growth temperature in MBE is commonly between 400°C and 700°C, which is far higher than the annealing temperature of typically 100°C–200°C during the ion-slicing. Naturally, thermal strain/stress will be introduced during the heating processes and it is one of the most probable reasons to cause the delamination.

Fig. 1.

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Fig. 1. (a) Optical microscope photo of a B2 sample surface with delamination after deoxidation at about 600°C. (b)–(d) 3D model of the three structures studied. Panels (b) is the overall structure and panels (c) and (d) are zoomed-in view of structure A and structure B1 & B2, respectively. The color indicates the absolute value of the stress component σxx at 600°C, and the III–V in panel (d) is taken from structure B2. The lateral dimension of the structure is 10 mm× 10 mm. The layer thicknesses are summarized in Table 1 and some key material parameters in Table 2.

In this work, the strain/stress in three structures of InPOI and GaAsOI at an MBE growth temperature is modeled and simulated by finite element method (FEM). Different layers above the Si wafer show different strain/stress polarities while the absolute value always increases with temperature. The stress in the Al₂O₃ layer is found to be of the most potential risk. Some samples have been characterized and the simulations are in consistent with the experimental results.

Three material structures, shown in Figs. 1(b)–1(d) with the detailed layer information summarized in Table 1, have been studied in this work. Structure A is similar to the structure reported in Ref. [13], which is 450-nm ion-sliced InP thin film bonded on a SiO₂/Si substrate. The detailed fabrication process can be found in Ref. [13]. The major difference between structures B and A is that an additional Al₂O₃ layer is added between the SiO₂ layer and the III–V template layer to increase adherence. The III–V template layer of structure B1 is InP and that of B2 is GaAs. The detailed information on how to fabricate the B structures using low temperature ion-slicing will be published elsewhere. All structures have been utilized as substrates to grow III–V optoelectronic materials and devices by MBE. The III–VOI wafers were cut into 10 mm× 10 mm pieces and adhered to 4-inch Si wafers by indium. During the deoxidation and epitaxy processes, the samples were heated to normal III–V MBE temperatures around 500°C–600°C. All samples exhibited delamination to different extents. Figure 1(a) shows an example of a B2 sample surface after deoxidation at 600°C in MBE with rectangle-like shapes captured by optical microscope. This sample was later characterized by a JEOL scanning electron microscope (SEM) at 15 kV.

Table 1.

Table 1.

Table 1. Layer information of the three structures. . Structure Si SiO2 Al2O3 III–V A 500 μm 500 nm 450-nm InP B1 500 μm 500 nm 20 nm 450-nm InP B2 500 μm 500 nm 20 nm 450-nm GaAs

Table 1. Layer information of the three structures. .

Table 2.

Table 2.

Table 2. Key material parameters utilized in the simulation. . Material Coefficient of thermal expansion/10−6 K−1 Thermal conductivity/(W/(m⋅K)) Young’s modulus/GPa Poisson ratio Si 2.6 130 170 0.28 SiO2 0.5 1.4 70 0.17 Al2O3 6.5 35 400 0.22 InP 4.6 68 61.1 0.36 GaAs 5.7 33 85.9 0.31

Table 2. Key material parameters utilized in the simulation. .

The heat transfer and strain/stress resulting from the differences in thermal expansion coefficients of each relevant layers in the three structures when heated to different temperatures in MBE were investigated by FEM. The three-dimensional (3D) material model of the three structures is shown in Figs. 1(b)–1(d). The simulated structure is square shaped with a side length of 10 mm which is the same as the real sample size for MBE growth. Heat transfer process and mechanics were both included to study the temperature and strain/stress distribution at different time and temperatures. The strain in the following context is defined as

Several assumptions are made to simplify the physical model and numerical simulations.

First, the materials involved in the study are assumed to be isotropic and obey the continuum elasticity theory. It has been shown that these assumptions provide high enough accuracy on strain/stress analysis for III–V structures even in nanoscale.^[15,16]

Second, the initial strain/stress was assumed to be zero at room temperature in the whole structure. The bottom surface is constrained in a way that it can freely deform laterally while no deformation is allowed in the vertical direction. Thus, the situation that the bottom surface of the samples is adhered to a Si wafer is validly simulated.

Third, it should be noted that the III–VOI has a crystal/amorphous interface. This implies that the thin III–V film on SiO₂ or Al₂O₃ behaves like a free standing substrate template to some extent depending on the bonding strength at the interface as well as the viscosity of the amorphous layer at the growth temperature. If it is a fully free standing template, it can be modeled as a compliant substrate^[17] implying that the III–V template can expand/contract horizontally with respect to the underneath amorphous layer to accommodate the overall strain. In such a case, the generated threading dislocations upon strain relaxation will propagate downward terminating at the crystal/amorphous interface while the epitaxial structure above the template is free from threading dislocations and resumes high material quality. In this work, we assume the interface is rigid (equivalent to very strong bonding). The simulated temperature is lower than the glass transition temperatures of SiO₂ and Al₂O₃.^[18] Therefore, the compliant effect is neglected and the III–VOI can be modeled in a similar way like a lattice mismatched heterostructure on a conventional crystal substrate.

Finally, we employ the PB model to estimate critical thickness of the epitaxial layers on III–VOI. The PB model is based on the energy balance between the strain energy (fully strained) and the dislocation energy (fully relaxed), and is not a thermodynamic model predicting the onset of initial strain relaxation by forming the first dislocation. The well-known Matthews–Blakeslee (MB) model^[19] is based on the force balance to predict the onset of strain relaxation (thus critical thickness) and is equivalent to the thermodynamic model. The MB model predicts a much smaller value of critical thickness compared with that of PB model, and the difference increases for small misfit. During practical epitaxy, there exists a kinetic barrier for initial dislocations gliding to relax partial strain due to the limited growth temperature, and strain relaxation is delayed, in particular when the growth temperature is low. Therefore, it is possible to “extend” the critical thickness beyond the value predicted by the MB model at a reduced growth temperature. On the other hand, for any experimental tool to detect dislocations, there is always a resolution indicating the minimal detectable number of dislocations, e.g., about 10⁴ cm⁻²–10⁵ cm⁻² for TEM. For the above reasons, the critical thicknesses predicted from the MB model has been found to fit experimental values for small misfit.^[17] In this work, we use the MB model to estimate critical thickness since the strain induced by thermal mismatch is not big.

The properties of the single crystals involved in the study, i.e., Si, GaAs, and InP are well determined while those for the dielectrics, i.e., SiO₂ and Al₂O₃, vary depending on deposition methods and conditions. The ones in this simulation are chosen from the most common values of atomic layer deposition (ALD) deposited thin films close to our experiment condition.^[20] The shear strain/stress components were found orders of magnitudes smaller than the in-plane ones. In the following sections, only the in-plane strain/stress components of ε_xx/σ_xx are discussed, unless specified. When discussing the critical conditions, strain is commonly utilized for the single crystals, i.e., Si, GaAs, and InP, while stress is usually mentioned for the dielectrics, i.e., SiO₂ and Al₂O₃.

In summary, strain and stress analyses were carried out for three III–VOI structures fabricated experimentally by ion-slicing as the substrate for the growth of optoelectronic devices on Si. The thermal strain/stress in InPOI at normal MBE growth temperature imposes basically little risk for all optoelectronic devices and some risk for thick devices like VCSEL and QCL if grown by MOCVD. GaAsOI is more risky than InPOI with a critical thickness of about 6 μm and 4 μm at 600°C and 750°C, respectively. The Al₂O₃ layer was intended to increase the adherence while it brings in the largest risk. The stress in Al₂O₃ is over 1 GPa which is much higher than the critical stress for interfacial fracture. InPOI without Al₂O₃ layer (structure A) is more suitable among the three structures as the substrate for the growth of Si-based laser or the platform for optoelectronic integration on Si.